VHDL Code for 2421 Counter

Design a 2421 Counter in VHDL programming by Using Filp Flops. Here VHDL code given below which use T – Filp Flop to design a 2421 Counter.

Code :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity tcounter2421 is port(clk,rst:in std_logic; q,qbar:inout std_logic_vector(3 downto 0)); end tcounter2421; architecture Behavioral of tcounter2421 is component tffl is port(t,rst,clk:in std_logic; q,qb:out std_logic); end component; signal k,l,m:std_logic; begin k<=q(0)and ((not q(2))or (not q(1)) or q(3)); l<=q(0) and (((not q(2)) and q(1))or q(3)); m<=q(1) and q(2) and q(0); a1:tffl port map('1',rst,clk,q(0),qbar(0)); a2:tffl port map(k,rst,clk,q(1),qbar(1)); a3:tffl port map(l,rst,clk,q(2),qbar(2)); a4:tffl port map(m,rst,clk,q(3),qbar(3)); end Behavioral;

T Filp Flop :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity tffl is port(t,rst,clk:in std_logic; q,qb:out std_logic); end tffl; architecture Behavioral of tffl is begin process variable x:std_logic:='0'; begin wait on clk ; if (clk' event and clk='1') then if rst='1' then x:='0'; elsif t='1' then x:=not x; else x:=x; end if; end if; q<=x; qb<=not x; end process; end Behavioral;